1. Field of the Invention
This invention relates generally to data processing systems and more particularly to data processing systems having a plurality of central processing units.
2. Description of the Related Art
In order to increase the processing capability of data processing systems, one technique has been to couple additional central processing units to the data processing system. The ability to select the number of central processing units in a data processing system permits an efficient matching of the capabilities of the system to the data processing requirements. Data processing having a plurality of central processing systems typically have one of two configurations. Referring now to FIG. 1A, a data processing system 10 having a plurality of central processing units, according to a first implementation found in the related art, is shown. The data processing system 10 includes a plurality of central processing units 11-12 coupled to a system bus 19. The central processing units 11-12 perform the actual manipulation of data groups under control of operating and user software programs. The main memory unit 16, also coupled to the system bus 19, stores the data and program signal groups which are currently being used by the central processing units. The input/output processing units 14-15, coupled to the system bus 19, include devices for storage of large quantities of data and program signal groups, e.g., disk storage devices, terminals for the entry of data by system users, and communication devices for exchange of data and program signal groups with remote locations. The system bus 19 provides the principal path for the exchange of data and program signal groups between the components of the data processing system 10.
Referring next to FIG. 1B, a second implementation of a multiprocessor data processing system, according to the related art, is shown. Generally, the same components are available to perform the processing functions as in FIG. 1A except that the components are coupled by a memory control unit 14 instead of by the system bus 19. The memory control unit 14 is typically an electronic switch providing the coupling of the data processing system 10' components in response to control signals. The memory control unit 14 can also provide functionality, such as conflict resolution, that would typically be distributed in the bus oriented data processing system.
The data processing systems of FIG. 1A and FIG. 1B are typically implemented in the related art such that the central processing units are homogeneous. In a homogeneous data processing system, the operating systems are the same or similar, the implementing apparatus is the same or similar and the operations performed on apparatus external to the data processing system is the same or similar. Even though the central processing units are homogeneous, substantial efforts are employed to prevent conflicts between the central processing units, thereby preventing conflicts between different activities for the data processing system resources. For example, one of the central processing systems can be selected to allocate resources and tasks among the plurality of central processing units. The resources of the system are the storage devices, terminals, main memory locations and other data processing facilities to which a central processing unit has access for the purpose of performing the data processing functions. This relationship is generally referred to as the master/slave relationship because of the control asserted by the selected processor. However, some data processing systems can be designed wherein the central processing units, operating under control of the same operating system, can operate under as equal members (as contrasted with the master/slave relationship) of the data processing system. The following references provide examples of the way in which a plurality of central processing units can be incorporated in a data processing system without a master/slave relationship while avoiding system resource access conflicts.
In U.S. Pat. No. 3,631,405, issued Dec. 28, 1971, entitled SHARING OF MICROPROGRAMS BETWEEN PROCESSORS and invented by G. S. Hoff and R. P. Kelly, two microprogrammed processing units share control elements that permit sharing of microprogram repertoires. By appropriate invocation of the operating system, the control signals from a first microprogrammed processing unit are transferred to the second microprogrammed processing unit. In fact, this configuration can best be described as a single processing unit with resources allocated by a supervisor controlled operating system. The use of a supervisor program as well as the coupling between the two processing units distinguishes this configuration from the peer processing unit relationship described in the present invention.
In U.S. Pat. No. 4,131,941, issued Dec. 26, 1978, entitled LINKED MICROPROGRAMMED PLURAL PROCESSOR UNIT and invented by H. L. Siegel, G. F. Muething, Jr., and E. J. Radkowski, a configuration of a plurality of processors is described that permits the processors to act independently or to be reconfigured so that a master/slave relationship can be invoked. The plurality of processors are linked together and, even when operating in a mode described as being independent, are not independent but subject to a supervisory control structure for configuration determination and for allocation of activity. Of course, the control of the allocation of activities implies the control of the allocation of resources. In addition, the data processing system described by this U.S. Patent, either has one operating system or a plurality of identical operating systems. The invention of the U.S. Patent appears to be best described as a single data processing system with a controllable configuration. The present invention is directed to central processing units having different operating systems that can function independently.
In U.S. Pat. No. 4,200,930, issued on Apr. 29, 1980, entitled ADAPTER CLUSTER MODULE FOR DATA COMMUNICATIONS SUBSYSTEM invented by R. L. Rawlings and R. D. Mathews, a host processing unit can have a plurality data communications subsystems coupled thereto for performing routine communications functions with incoming and outgoing signals. Although the data communications subsystems are capable, in case of a failure of the host processing unit, of continuing communications, the role of the host processing unit to the data communications subsystems is clearly that of a master/slave relationship. The peer processor relationship is not applicable because the data communications subsystems do not have access to all the resources available to the host processing unit.
In U.S. Pat. No. 4,722,048, issued on Jan. 26, 1988, entitled MICROCOMPUTER SYSTEM WITH INDEPENDENT OPERATING SYSTEMS, invented by T. S. Hirsch, J. W. Stonier and T. 0. Holtey, two processors, an LSI-6 processor with a MOD400 operating system and an Intel 8086 processor with either and MS-DOS or a CPM-86 operating, share the processing responsibilities (a Motorola 6809 microprocessor is also included, but generally functions as an input/output controller). The LSI-6 processor has memory space that is not accessible to the Intel 8086 processor. In addition, the input/output operations performed by the 6809 microprocessor can be initiated only by the LSI-6 processor, so that the Intel 8086 has access to this resource only through the intervention of the LSI-6 processor, a form of a master/slave relationship.
In U.S. Patent Application Ser. No. 06/859,593, filed on May 5, 1986, entitled MULTIPROCESSOR SYSTEM ARCHITECTURE, invented by C. Fiacconi et al, the communication of two processors is described. In this application, the sharing of memory without interference is accomplished by controlling buses associated with each processor system. The buses are coupled to particular areas of memory and, for one processor to access the memory dedicated to the second processor, the bus of the first processor is coupled to the bus of the second processor. Apparatus associated with each bus controls the ability of the other processor to access the system bus, thereby effectively limiting access of each processor to the system resources.
More recently, interest has been demonstrated in data processing systems having a plurality of central processing units functioning with non-homogeneous (generally incompatible) characteristics. The availability of non-homogeneous central processing units can be particularly advantageous to a system user providing the availability of a plurality of program repertoires. Ideally, all of the central processing units should have a peer relationship, i.e., should be capable of accessing all resources without the benefit of auxiliary protection mechanisms described in relation to the related art and without having a master/slave relationship in which one central processing unit controls all the activity and allocation of resources. Many central processing systems do not have the necessary hardware and/or software functionality to enforce allocation of resources. Non-the-less, the peer relationship between central processing units is a desirable multiprocessor relationship, allowing easy expandability of the processing system.
A need has been felt for technique that permits any central processing unit to be coupled to a data processing system even though necessary the mechanisms for enforcement of resource allocation are not present.